Memory such as an EEPROM or a flash memory device contains at least one array of memory cells that include floating gate transistors. The floating gate transistors store data as an electron charge trapped on an isolated floating gate. The amount of trapped charge in a floating gate transistor determines the threshold voltage, and data can be written in or read from a memory cell by setting or programming the threshold voltage of the floating gate transistor in the memory cell. If the methods for setting and determining the threshold voltages are sufficiently accurate and dependable, the memory array will be reliable, and each memory transistor may store multiple bits of data in each memory cell. However, stored data values read from a memory cell may drift from one reading to the next because of variations in the operating parameters of the memory or because of the use and history of the memory.
One difficulty encountered when setting or programming a threshold voltage is variations in operating parameters such as the temperature and supply voltage of the memory. If the operating parameters of the memory during a read operation differ from the operating parameters when the data were written or programmed, the threshold voltage when read from a memory cell can differ from the threshold voltage as written. In addition, charge leakage from the floating gate, memory cell disturb and endurance history, degradation, or the number of write and erase cycles for an individual memory cell in comparison to other memory cells in the array, may affect the characteristics of a memory cell and can change the threshold voltage. Also, due to variances in manufacturing processes, including the location of a memory array on a manufacturing wafer, variations in the structure of each memory cell, or the location of a memory cell within the array, one memory cell may have different characteristics in comparison to another memory cell. Accordingly, to maintain reliability of a memory device, or to support a multi-bit-per-cell memory, variations in operating parameters must be considered to avoid data errors in a memory array or memory device.
Referring to FIG. 1, a typical prior art memory arrangement 100 contains a memory bank or memory array 110. The memory array is further segmented or arranged into one or more individual sectors 116. The memory array 110 contains an array of storage cells 112 (or core array) and an array of reference cells 114 arranged in an array. A single memory device may contain multiple memory banks or memory arrays 110. The array of reference cells 114 is typically arranged or located at the edge or edges of the storage cell array 112. Storage cells 112 and reference cells 114 are accessed or addressed by a row decode circuit 121 and a column decode circuit 123. Generally, the row 121 and column decode 123 circuits activate or access the memory array via word lines and bit lines (not shown) that interconnect storage and reference cells in the memory array. Other control circuits such as a read and sense circuit 131 or a voltage supply circuit (not shown) or ramp circuit (not shown), are used to access, write or program, erase, and read the storage and reference cells.
In the prior art, a selected storage cell in the array of storage cells 112 may be physically apart from the reference cell array 114, as illustrated in FIG. 1. A storage cell and reference cell may have different operating characteristics during a read operation due to any one of the following factors: a) different physical location, b) different structure (due to manufacturing variances), c) different bias voltages on the storage cell sensing gate during a read operation, d) different erase and write or programming environments during a write or programming operation, and e) different number of write cycles or different history thus producing a different degree of degradation to an individual cell. The variance from any one of the above factors may cause the characteristics of a storage cell and a reference cell to drift so a reference cell does not match a storage cell in the core array. Generally, the further a storage cell is from a reference cell, the above factors will vary more and have a greater effect on the operating characteristics of a storage cell and reference cell. In summary, there are multiple variables that may change the operating characteristics of one memory cell in comparison with another memory cell. Differences between a storage cell and a reference cell may cause a stored value in a storage cell to be incorrectly read causing a data error or read failure.
Generally, reference cells are used to maintain a consistent relative measurement standard within a memory device. However, the reference cells may not accurately track other memory cells within the memory device. U.S. Pat. No. 6,094,368 to Ching entitled “Auto-Tracking Write and Read Processes for Multi-Bit-Per-Cell Non-Volatile Memories” has a disadvantage of having reference cells grouped at the edge of a memory cell array, and does not include a method to compensate for the endurance history for the memory cells. U.S. Pat. No. 6,819,589 to Aakjer entitled “Flash Memory With Pre-Detection for Data Loss” implements a second read operation using a second reference or bias voltage to compensate for retention variability in a memory array, but has a disadvantage of negatively affecting the memory's performance when implementing a second or third read operation, and then a refresh operation for memory cells that are weakly programmed. What is needed is a method to compensate or eliminate the variations in operating parameters to provide reliable storage of single bit data or multiple bit data stored in each memory cell within a memory array that does not reduce the overall performance of a memory device.
One approach to account for variations in operating parameters, charge leakage, and degradation is to use a band of threshold voltages that is sufficiently wide to cover the anticipated variations in the threshold voltages read for each data value stored in each memory cell. However, trade-offs must also be considered, for example, to improve programming speed. Also, using a wide range of threshold voltages of a memory cell is limited, since implementing wide bands for each data value reduces the number of bits that can be stored in each memory cell. Accordingly, a reliable memory cell or a multi-bit memory cell is sought that accurately accounts for or compensates for variations in operating parameters and provides a reliable operation or provides a maximum number of data bits per memory cell.